A 10 Gb/s low-power serdes receiver based on a hybrid speculative/SAR digitization technique

This paper presents a DSP-based SerDes reα that utilizes a hybrid speculative/successive-approxims register (SAR) analog-to-digital converter (ADC) to digitize data at the receiver´s analog front-end. The proposed digitize technique addresses the high-power drawback of conventi flash-based ADCs used in sampling-based wireline recei´ while allowing for digital equalization and data recover; 10 Gb/s through five time-interleaved channels. The receiver is designed and laid out in a 65 nm CMOS process. The occupies 1.53 mm² , and based on simulation results, it consu 263 mW from a 1 V core supply.