Biologically-inspired digital circuit for a self-organising neural network

This work presents the design and characterisation of a fully digital VLSI ASIC neuron cell. The 25 mm² IC die was fabricated in a 1.2 micron CMOS technology and has 5 k equivalent gates. Its architecture was designed to implement neural networks based on the Self-Organising Feature Maps (SOFM) with enhanced performance in high-speed applications. Various learning parameters can be programmed, as gain curves and neighbour cells interaction, fostering network convergence. A top-down IC design methodology was adopted, with high-level modelling using ANSI-C language and behavioural VHDL, digital simulation and synthesis from a RTL VHDL description. The synthesised circuits were mapped and optimised to the fabrication technology. Afterwards, the layout, back annotation, circuit parameter extraction and post layout simulation were done. After fabrication, we have measured the performance, obtaining good results