DocumentCode :
1987096
Title :
All digital phase-locked loop using active inductor oscillator and novel locking algorithm
Author :
Huang, Tzu-Chi ; Huang, Hong-Yi ; Liu, Jen-Chieh ; Cheng, Kuo-Hsing ; Luo, Ching-Hsing
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fYear :
2011
fDate :
15-18 May 2011
Firstpage :
486
Lastpage :
489
Abstract :
A fast locking all-digital phase-locked loop (ADPLL) with the active inductor oscillator is proposed. An LC-tank DCO with a tunable active inductor can obtain a wider operational frequency range, smaller area and higher signal quality. The proposed frequency and phase locking algorithm can achieve good jitter performance, high frequency accuracy, and low circuit complexity. The ADPLL is designed using a 0.18 um CMOS process. The operational frequency range of the ADPLL is from 318 MHz to 458 MHz. The RMS and the peak-to-peak jitters at 402 MHz are 4.2 ps and 94 ps, respectively. The core size is 390×390 um2. The power consumption is 5.4 mW at 416 MHz.
Keywords :
CMOS integrated circuits; digital phase locked loops; inductors; jitter; oscillators; CMOS; LC-tank DCO; active inductor oscillator; all digital phase-locked loop; frequency 318 MHz to 458 MHz; jitters; locking algorithm; power 5.4 mW; size 0.18 mum; size 390 mum; time 4.2 ps; time 94 ps; Active inductors; Jitter; Phase frequency detector; Phase locked loops; Synchronization; Tuning; Varactors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location :
Rio de Janeiro
ISSN :
0271-4302
Print_ISBN :
978-1-4244-9473-6
Electronic_ISBN :
0271-4302
Type :
conf
DOI :
10.1109/ISCAS.2011.5937608
Filename :
5937608
Link To Document :
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