Variable-duty-cycle scheduling in double-edge-triggered flip-flop-based high-level synthesis

This paper proposes a novel high-level synthesis (HLS) using double-edge-triggered flip-flops (DETFF) as memory elements. The duty-cycle is a key factor in the HLS. To utilize the duty-cycle radically, a variable-duty-cycle (VDC) mechanism is built into the HLS, which is captured by a new HLS task named VDC scheduling. As the first step for DETFF-based HLS, the clock-period minimization problem is formulated, and solved by a graph-based algorithm. The experimental results support the effectiveness of the algorithm.