Title :
TG Master-Slave FFs: High-speed optimization
Author :
Consoli, Elio ; Palumbo, Gaetano ; Pennisi, Melita
Author_Institution :
Dept. of Electr., Electron. & Syst. Eng., Univ. of Catania, Catania, Italy
Abstract :
In this paper we show that, when dealing with transmission-gate based Master-Slave FFs, a reconsideration of the usual approach for high-speed design is worthwhile to improve energy-efficiency. By splitting such FFs in two separately optimized sections and then reconciling the results, the emerging design always outperforms that resulting from the employment of a classical procedure assuming FFs as a whole continuous path.
Keywords :
flip-flops; logic gates; optimisation; TG master-slave FF; continuous path; flip-flops; high-speed design; high-speed optimization; transmission gate; Capacitance; Delay; Flip-flops; Logic gates; Master-slave; Optimization; Transistors;
Conference_Titel :
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location :
Rio de Janeiro
Print_ISBN :
978-1-4244-9473-6
Electronic_ISBN :
0271-4302
DOI :
10.1109/ISCAS.2011.5937625