DocumentCode :
1987495
Title :
RF noise modelling of 0.25 /spl mu/m CMOS and low power LNAs
Author :
Vanoppen, R.R.J. ; de Maaijer, L.M.F. ; Klaassen, D.B.M. ; Tiemeijer, L.F.
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
fYear :
1997
fDate :
10-10 Dec. 1997
Firstpage :
317
Lastpage :
320
Abstract :
A prototype 0.5 /spl mu/m CMOS LNA with a noise figure of 2.2 dB and a gain of 16.9 dB at 900 MHz at a power consumption of 1.8 mW is reported. This result, and the noise figures obtained on 0.25 /spl mu/m CMOS, are reproduced by simulations, confirming that RF noise modeling can be accurately performed using our public domain MOS Model 9. Simulations are presented for similar LNAs realized in standard CMOS processes with gate dimensions down to 0.13 /spl mu/m. Provided high Q matching circuitry is used, for the latter gate length a noise figure of only 1.1 dB and 27 dB gain at 1800 MHz, at a minimal power consumption of only 0.2 mW, is predicted.
Keywords :
CMOS analogue integrated circuits; integrated circuit modelling; integrated circuit noise; radiofrequency amplifiers; 0.13 micron; 0.25 micron; 0.5 micron; 1.1 dB; 16.9 dB; 1800 MHz; 2.2 dB; 27 dB; 900 MHz; CMOS IC; MOS Model 9; RF noise model; gain; high Q matching circuitry; low power LNA; noise figure; power consumption; simulation; Circuit simulation; Circuit testing; Frequency measurement; Integrated circuit noise; MOS devices; Noise figure; Noise measurement; Power measurement; Radio frequency; Semiconductor device modeling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International
Conference_Location :
Washington, DC, USA
ISSN :
0163-1918
Print_ISBN :
0-7803-4100-7
Type :
conf
DOI :
10.1109/IEDM.1997.650390
Filename :
650390
Link To Document :
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