• DocumentCode
    1987531
  • Title

    Area-efficient fast scheduling schemes for MVC prediction architecture

  • Author

    Choi, Minsu ; Kim, Jinsang ; Cho, Won-Kyung ; Burm, Jinwook

  • Author_Institution
    Dept. of Electron. & Radio Eng., Kyung Hee Univ., Yongin, South Korea
  • fYear
    2011
  • fDate
    15-18 May 2011
  • Firstpage
    575
  • Lastpage
    578
  • Abstract
    While multi-view video system offers users various three-dimensional scenes, its hardware architecture requires more power consumption, chip size and processing time. Each view in Group of Group of Pictures (GoGoP) has different frame structure and different number of reference frames. The multi-view video coding (MVC) performance heavily relies on the frame scheduling architecture for motion estimation (ME) and disparity estimation (DE). Therefore, we need to develop efficient frame scheduling schemes for MVC. In this paper, we propose two frame scheduling schemes: hardware resource aware scheduling (HRaS) and buffering time aware scheduling (BTaS). In the proposed scheduling schemes, the GoGoP is represented by a graph in which edges represent relationship between reference frames and current frames. HRaS relocates frames in GoGoP so that total hardware resources for MVC prediction are reduced. BTaS relocates the frames based on the number of edges so that prediction time and buffering time of the frames are reduced. Through experimental results, we verified the efficiency of the proposed scheduling architectures in terms of power dissipation, area, MVC prediction time, and buffering time.
  • Keywords
    motion estimation; scheduling; video coding; BTaS; DE; GoGoP; HRaS; ME; MVC prediction architecture; area-efficient fast scheduling scheme; buffering time aware scheduling; disparity estimation; frame scheduling architecture scheme; group of group of picture; hardware resource aware scheduling; motion estimation; multiview video coding prediction architecture; power consumption; power dissipation; prediction time; Bandwidth; Computer architecture; Estimation; Hardware; Indexes; Multiplexing; Streaming media;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
  • Conference_Location
    Rio de Janeiro
  • ISSN
    0271-4302
  • Print_ISBN
    978-1-4244-9473-6
  • Electronic_ISBN
    0271-4302
  • Type

    conf

  • DOI
    10.1109/ISCAS.2011.5937630
  • Filename
    5937630