Fault-tolerant hypercube using linear arithmetic code

Author

Krishnan, D.C. ; Shiao, J.C. ; Han, J.Y.

Author_Institution

Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA

fYear

1989

fDate

14-16 Aug 1989

Firstpage

936

Abstract

A concurrent error detection and correction scheme using linear arithmetic code (LAC) is proposed for matrix operations on a hypercube multiprocessor system. The method uses the concept of error patterns to derive a set of linear check codes suitable for matrix operations. It can detect and correct errors caused by single communication line or single processor fault

Keywords

fault tolerant computing; hypercube networks; concurrent error correction scheme; concurrent error detection; correct errors caused by single communication line; error patterns; hypercube multiprocessor system; linear arithmetic code; linear check codes; matrix operations; single processor fault; Arithmetic; Broadcasting; Computer errors; Costs; Error correction codes; Fault detection; Fault tolerance; Hypercubes; Los Angeles Council; Multiprocessing systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1989., Proceedings of the 32nd Midwest Symposium on

Conference_Location

Champaign, IL

Type

conf

DOI

10.1109/MWSCAS.1989.102008

Filename

102008

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1987538