DocumentCode :
1987693
Title :
Scaling the Multifluid PPM Code on Blue Waters and Intel MIC
Author :
Woodward, Paul R. ; Jayaraj, Jagan ; Pei-Hung Lin ; Knox, Michael ; Hammond, S.D. ; Greensky, James ; Anderson, Sarah E.
Author_Institution :
Lab. for Comput. Sci. & Eng., Univ. of Minnesota, Minneapolis, MN, USA
fYear :
2013
fDate :
15-16 Aug. 2013
Firstpage :
64
Lastpage :
72
Abstract :
Over the course of the last year, we have worked to adapt our multifluid PPM code to run well at scale on the Blue Waters machine at NCSA as well as on networks of Intel Xeon Phi coprocessors. The work on Blue Waters has been in collaboration with Cray and that with Intel´s MIC co-processors in collaboration with Intel. Our starting point for this work was a version of the code that was developed to run well at scale on the Los Alamos Roadrunner machine. We therefore began with an implementation that was designed to take advantage of heterogeneous processor systems. In this paper, we will discuss scaling issues encountered on Blue Waters as well as issues encountered with Intel´s MIC co-processors. We present the code structure that we developed in this work, beginning with its parallel implementation using heterogeneous MPI processes and proceeding to its parallel implementation on a single multi- or many-core CPU. We also present a sampling of results from a simulation on Blue Waters on a 1.18 trillion cell grid that ran at a sustained rate in 32-bit precision of 1.5 Pflop/s.
Keywords :
computational fluid dynamics; coprocessors; message passing; multi-threading; multiprocessing systems; parallel machines; Blue Waters machine; Cray; Intel MIC coprocessors; Intel Xeon Phi coprocessors; Los Alamos Roadrunner machine; NCSA; code structure; heterogeneous MPI processes; heterogeneous processor systems; many-core CPU; multicore CPU; multifluid PPM code scaling; multithreading; parallel implementation; scaling issues; word length 32 bit; Bandwidth; Hardware; Instruction sets; Message systems; Microwave integrated circuits; Solids; System-on-chip; high performance computing; multicore processors; petascale computing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Extreme Scaling Workshop (XSW), 2013
Conference_Location :
Boulder, CO
Type :
conf
DOI :
10.1109/XSW.2013.13
Filename :
6805044
Link To Document :
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