A 160-Mhz 45-mW Asynchronous Dual-Port 1-Mb CMOS SRAM

A 160-Mhz 45-mW asynchronous dualport 1-Mb CMOS SRAM is described. A minimum read access time of 4.26ns is achieved, with an active power figure of 31 mW, data retention capability at 0.1 V VDD across all skews with varied temperature, and yet consume a standby power of only 80nW. Simulation results show that the circuit functions properly over a wide range of Process, Voltage & Temperature (PVT) corners. SRAM was custom designed using TSMC CMOS 0.25μm 1P5M Salicide process with a total die size of approximately 115mm².