Title :
22nm technology yield optimization using multivariate 3D virtual fabrication
Author :
Cipriany, B. ; Jagannathan, B. ; Costrini, G. ; Noemaun, A. ; Onishi, Kohei ; Narasimha, S. ; Zhang, Boming ; Sheraw, C. ; Meiring, J. ; Kumar, Manoj ; Nummy, K. ; Zhan, N. ; Nanjundappa, H. ; Norum, J. ; Furkay, S. ; Malik, Rohit ; Agnello, P. ; Fried, D
Author_Institution :
Semicond. R&D Center, IBM, Hopewell Junction, NY, USA
Abstract :
We present a technology development methodology that relies on 3D virtual fabrication to rapidly improve yield by increasing tolerance to multilevel process variation. This methodology has been successfully implemented in the development and yield ramp of high-performance 22nm SOI CMOS technology. Based on virtual metrology, dedicated testsite structures were designed and implemented, with electrical results corroborating virtual findings, validating the methodology. This 3D virtual fabrication technique was used to implement a delicate process change, and the same testsite structures validated the improved process window yield.
Keywords :
CMOS integrated circuits; integrated circuit measurement; integrated circuit testing; integrated circuit yield; silicon-on-insulator; SOI CMOS technology; multilevel process variation; multivariate 3D virtual fabrication; process window yield; silicon-on-insulator; size 22 nm; technology yield optimization; test site structures; virtual metrology; yield ramp; Calibration; Fabrication; Logic gates; Metrology; Optimization; Solid modeling; Three-dimensional displays; 22nm; CMOS; modeling; n-p transition; testsite; virtual fabrication; virtual metrology; yield optimization;
Conference_Titel :
Simulation of Semiconductor Processes and Devices (SISPAD), 2013 International Conference on
Conference_Location :
Glasgow
Print_ISBN :
978-1-4673-5733-3
DOI :
10.1109/SISPAD.2013.6650583
