Title :
Double patterning: Simulating a variability challenge for advanced transistors
Author :
Evanschitzky, P. ; Burenkov, Alex ; Lorenz, Juergen
Author_Institution :
Fraunhofer Inst. for Integrated Syst. & Device Technol. IISB, Erlangen, Germany
Abstract :
In this paper a comprehensive study of the impact of variations resulting from double patterning lithography on SRAM performance is presented. In double patterning, feature sizes are reduced by splitting one mask level into two. Besides the increase of process complexity and costs a further penalty is the introduction of uncorrelated variations between the two incremental lithography steps employed.
Keywords :
SRAM chips; lithography; SRAM performance; advanced transistors; double patterning lithography; feature sizes; incremental lithography steps; mask level; process complexity; uncorrelated variations; variability challenge; Computational modeling; Lighting; Lithography; Logic gates; Random access memory; Resists; Transistors; 20nm gate length; Photo lithography; SOI CMOSFETs; SRAM; double patterning;
Conference_Titel :
Simulation of Semiconductor Processes and Devices (SISPAD), 2013 International Conference on
Conference_Location :
Glasgow
Print_ISBN :
978-1-4673-5733-3
DOI :
10.1109/SISPAD.2013.6650585
