Combining ISA extensions and subsetting for improved ASIP performance and cost

This paper presents a fine-grained configurable processor model used to generate image processing Application Specific Instruction Set Processors (ASIPs). A methodology to develop a minimal instruction set ASIP with the processor model is also proposed. The methodology is based on using specialized instructions in conjunction with Instruction Set Architecture (ISA) subsetting to reduce hardware costs and improve execution time. The performance of an FPGA implementation of the proposed processor model is measured for a two-dimensional Gaussian filter and results are compared to a popular commercial soft core processor. With ISA subsetting and specialized instructions, the proposed processor uses up to 45% fewer slices while achieving a 1.57× speedup.