• DocumentCode
    1987936
  • Title

    Gate-Misalignment-Effect Related Capacitance Behavior of a 100nm Double-Gate FD SOI NMOS Device with n+/p+Poly Top/Bottom Gate

  • Author

    Kuo, J.B. ; Hsu, C.H. ; Yang, C.P.

  • Author_Institution
    Dept of Electrical Engineering, Rm 338, National Taiwan University, Taipei, Taiwan 106-17. Email: j.kuo@ieee.org
  • fYear
    2005
  • fDate
    19-21 Dec. 2005
  • Firstpage
    397
  • Lastpage
    400
  • Abstract
    This paper reports the gate-misalignment-effect related capacitance behavior of a 100nm double-gate (DG) fully-depleted (FD) SOI NMOS device with the n+p+poly top/bottom gate. Based on the 2D simulation result, with the gate misalignment, the sudden fall in the gate-drain/source capacitance (CGD/CGS) of the device at VG=0.5V is mitigated due to the reduced hole accumulation/ depletion in the bottom channel controlled by the p+bottom gate with the increased fringing electric field effect.
  • Keywords
    Capacitance; Doping; MOS devices; Transistors; Very large scale integration; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices and Solid-State Circuits, 2005 IEEE Conference on
  • Print_ISBN
    0-7803-9339-2
  • Type

    conf

  • DOI
    10.1109/EDSSC.2005.1635290
  • Filename
    1635290
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1987936