A fast edge detection chip for robot vision systems

Summary form only given. A fast edge detector architecture and IC, based on a new edge follower algorithm, have been designed. The chip offers real-time processing with a limited amount of hardware due to the optimization of the critical path in the architecture. In this way, a complete frame (512×512) can be processed in about 400000 clock cycles, and a clock rate of up to 10 MHz has been achieved in a 3-μm double-metal CMOS technology. This chip offers online information such as edge location and orientation, which can be used for feature extraction and pattern recognition in the robot vision system. A novel architectural model, the multiplexed cooperating datapath architecture, has been adopted to obtain an efficient design with a minimal set of functional building blocks. The methodology is especially suited for recursive types of algorithms such as the edge follower. High throughput is achieved by optimizing the memory storage and by eliminating the communication bottlenecks with dedicated buses