Notice of Violation of IEEE Publication PrinciplesDesign of ultra-low power CMOS cells for temperature sensors in VLSI

Notice of Violation of IEEE Publication Principles

"Design of Ultra-low Power CMOS Cells for Temperature Sensors in VLSI,"
by V. Nath, R. Kumari, B.N. Das, R.N. Gupta, K.S. Yadav, L.K. Singh, T.T. Jeong
in the Proceedings of the International Conference on Emerging Trends in Electronic and Photonic Devices & Systems, 2009. ELECTRO \´09, Dec. 2009, pp. 116-119

After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE\´s Publication Principles.

This paper is a duplication of the original text from the paper cited below. The original text was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission.

Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following article:

"Ultra-low Power CMOS Cells for Temperature Sensors"
by C. Rossi and P. Aguirre
in the Proceedings of the 18th Annual Symposium on Integrated Circuits and System Design, ACM Press, 2005, pp. 202ߝ206

Temperature sensors and voltage references require cells that generate both PTAT (Proportional to Absolute Temperature) and NTC (Negative Temperature coefficient) voltages. We present a novel theoretical approach based on a quasi-constant current to obtain these voltages in standard CMOS technology using no resistors. These circuits are designed simulated using CADENCE analog and digital system design tools of 0.6 ??m CMOS technology. We performed measurements in a -43??C to 127??C temperature range which verify the expected results. The circuit draws under 50 nA from a 1.0 V to 1.6 V supply.