A maximal entropy digital chaotic circuit

This paper introduces a novel digital chaotic circuit that is capable of supporting both the maximum entropy requirements of a chaotic communication system and the hardware efficiency requirements of practical implementations. Moreover, since the circuits implement a discrete-time discrete- amplitude chaotic mapping, the circuit is capable of overcoming the traditional "hard" problem of chaotic circuit synchronization in communication systems by mapping it to the well understood problem of timing synchronization. The efficiency gains of this circuit come from extrapolation of the traditional chaotic properties to closed Galois fields, finite residue number system (RNS) arithmetic, and truncated conversion to a weighted number system.