DocumentCode :
1988406
Title :
Methodology to Evaluate the Robustness of Integrated Circuits under Cable Discharge Event
Author :
Lai, Tai-Xiang ; Ker, Ming-Dou
Author_Institution :
Institute of Electronic, National Chiao-Tung University, Hsinchu, Taiwan.
fYear :
2005
fDate :
19-21 Dec. 2005
Firstpage :
499
Lastpage :
502
Abstract :
Cable Discharge Event (CDE) has been the main cause which damages the Ethernet interface. The transmission line pulsing (TLP) system has been the most important method to observe electric characteristics of the device under human-body-model (HBM) ESD stress. In this work, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate the influence of CDE on the Ethernet integrated circuits, and the results are compared with conventional 100-ns TLP system. The experimental results have shown that the CDE robustness of NMOS device in a 0.25-μm CMOS technology is much worse than its HBM electrostatic discharge robustness.
Keywords :
CMOS technology; Circuit simulation; Distributed parameter circuits; Electric variables; Electrostatic discharge; Ethernet networks; MOS devices; Power cables; Robustness; Stress;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices and Solid-State Circuits, 2005 IEEE Conference on
Print_ISBN :
0-7803-9339-2
Type :
conf
DOI :
10.1109/EDSSC.2005.1635317
Filename :
1635317
Link To Document :
بازگشت