Circuit-level modeling of FinFet sub-threshold slope and DIBL mismatch beyond 22nm

We propose a way of modeling device variability in sub-threshold slope and DIBL at circuit-level using dependent voltage sources. The usual way of modeling variability using threshold voltage shift and drain current amplification is becoming inaccurate as new sources of variability appear in sub-22nm devices. Benchmark experiments on circuit level, using a set of 1000 TCAD-based 10nm-FinFet device models with mismatch as a reference, show systematic accuracy improvements on mean and standard deviation of 6T-SRAM cell stability metrics of up to 30 and 10 percentage scores, respectively.