Title :
Noise tolerance enhancement in low voltage dynamic circuits
Author :
Mazumdar, Kaushik ; Pattanaik, Manisha
Author_Institution :
ABV-Indian Inst. of Inf. Technol. & Manage., Gwalior, India
Abstract :
To address the noise reliability problem in deep submicron digital circuits, a new noise-tolerant dynamic circuit technique has been proposed here. The average noise threshold energy (ANTE) and the Delay normalized ANTE metrics have been used to quantify the noise immunity and speed efficiency. A 2 input AND gate has been designed and simulated using 0.18 micron BSIM3V3.3 technology to indicate that the proposed technique improves the ANTE and Delay normalized ANTE by 11.54X and 6.27X over the conventional domino circuit.
Keywords :
VLSI; digital integrated circuits; integrated circuit noise; integrated circuit reliability; logic gates; low-power electronics; 2-input AND gate; BSIM3V3.3 technology; average noise threshold energy; deep submicron digital circuits; delay normalized ANTE metrics; domino circuit; low-voltage dynamic circuits; noise reliability problem; noise-tolerance enhancement; noise-tolerant dynamic circuit technique; CMOS technology; Circuit noise; Circuit simulation; Coupling circuits; Delay; Feedback circuits; Logic gates; Low voltage; Power supplies; Very large scale integration; ANTE; Coupling Noise; Dynamic; Noise Tolerance;
Conference_Titel :
Emerging Trends in Electronic and Photonic Devices & Systems, 2009. ELECTRO '09. International Conference on
Conference_Location :
Varanasi
Print_ISBN :
978-1-4244-4846-3
DOI :
10.1109/ELECTRO.2009.5441166
