DocumentCode :
1988501
Title :
PDK development for 10nm III-V/Ge IFQW CMOS technology including statistical variability
Author :
Si-Yu Liao ; Towie, E.A. ; Balaz, D. ; Riddet, C. ; Binjie Cheng ; Asenov, Asen
Author_Institution :
Device Modelling Group, Univ. of Glasgow, Glasgow, UK
fYear :
2013
fDate :
3-5 Sept. 2013
Firstpage :
220
Lastpage :
223
Abstract :
From 3D Monte Carlo and drift diffusion TCAD simulations to compact models, we develop an early PDK of 10nm CMOS node technology employing co-integration of 15nm physical channel length III-V and Ge transistors. By taking into account the statistical variability, reliable predictions of the impact of variability on circuit performance and yield can be delivered to achieve variation aware design.
Keywords :
CMOS memory circuits; III-V semiconductors; Monte Carlo methods; SRAM chips; elemental semiconductors; germanium; logic design; quantum well devices; 3D Monte Carlo simulation; CMOS node technology; III-V/Ge IFQW CMOS technology; PDK development; circuit performance; circuit yield; compact models; drift diffusion TCAD simulation; impact of variability; physical channel length III-V transistors; size 10 nm; size 15 nm; statistical variability; variation aware design; CMOS integrated circuits; Integrated circuit modeling; Logic gates; MOSFET; SRAM cells; Semiconductor device modeling; CMOS; Compact Model; Ge; III-V; SRAM; Statistical Variability; Variation-Aware Circuit Design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Simulation of Semiconductor Processes and Devices (SISPAD), 2013 International Conference on
Conference_Location :
Glasgow
ISSN :
1946-1569
Print_ISBN :
978-1-4673-5733-3
Type :
conf
DOI :
10.1109/SISPAD.2013.6650614
Filename :
6650614
Link To Document :
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