Title :
On implementing large fault-tolerant binary tree architecture in WSI
Author :
Chau, Siu-Cheung
Author_Institution :
Dept. of Math. & Comput. Sci., Lethbridge Univ., Alta., Canada
Abstract :
A new layout scheme for fault-tolerant binary tree architecture in WSI with a high area utilization, short propagation delay, and short edge length is proposed. In the new layout scheme, the binary tree is partitioned into fault-tolerant modules. Each module can contain 3 active processors and k spares. That is, each fault-tolerant module can be connected to 4 other fault-tolerant modules. The new scheme can also be used to provide area efficient layout for previously proposed fault-tolerant binary tree architectures
Keywords :
VLSI; fault tolerant computing; multiprocessor interconnection networks; parallel architectures; trees (mathematics); WSI; active processors; fault-tolerant binary tree architecture; fault-tolerant module; fault-tolerant modules; high area utilization; layout scheme; short edge length; short propagation delay; Binary trees; Computer architecture; Computer science; Database machines; Dictionaries; Fault tolerance; Mathematics; Propagation delay; Topology; Very large scale integration;
Conference_Titel :
Computing and Information, 1993. Proceedings ICCI '93., Fifth International Conference on
Conference_Location :
Sudbury, Ont.
Print_ISBN :
0-8186-4212-2
DOI :
10.1109/ICCI.1993.315389
