A novel operating-point driven method for the sizing of analog IC

It is known that the operating-point driven (OPD) analog sizing methods have clear advantages compared with the sizing methods of directly using transistor width and length as the decision variables. However, new analog sizing algorithms using OPD technique in modern technologies have seldom been reported in recent years. One of the main reasons is that with the scaling down of the technologies, the transistor models are much more complex, which makes the available DC root solving algorithms and the look-up-table-based methods face significant challenges on accuracy, efficiency and memory requirements. Instead of solving the equations to find the width of transistors, interpolating in a pre-constructed look-up-table, or using regression methods, a novel method, called on-line interpolation operating-point driven (OIOPD), is proposed. OIOPD finds the width of the transistor by the interpolation of the width-current curve with already determined length and voltage biases. The lower and upper points to decide the interpolated value are generated by on-line simulations using the two extreme values of the width in a technology. Experimental results in 0.25μm, 0.18 μm and 90nm technologies show that OIOPD has 10 times improvement on accuracy, 300-1100 times improvement on efficiency compared with the available methods. In addition, no extra memory (e.g. the memory to save the look-up table) is needed. These advantages make OIOPD suitable for operating-point driven analog sizing methods in modern technologies. A practical analog sizing example using OIOPD is also provided.