A low-power 8-bit SAR ADC for a QCIF image sensor

Author

Özgün, Recep ; Lin, Joseph ; Tejada, Francisco ; Pouliquen, Philippe ; Andreou, Andreas G.

Author_Institution

Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA

fYear

2011

fDate

15-18 May 2011

Firstpage

841

Lastpage

844

Abstract

In this paper, we report on an 8-bit auto-calibrating successive-approximation-register (SAR) analog-to-digital converter (ADC) for ultra-low power image sensors. The fabricated design includes an on-chip bandgap voltage reference and a tunable clock generator in addition to the SAR ADC core circuitry. Aside from two power pins, the design uses only one extra pin to output the digitized samples serially. Power consumption for the design is 21μW at 0.8V supply voltage, and it is 32μW including ancillary circuits. The sampling rate varies from 370kS/s to 1.6MS/s depending on the supply voltage. The design occupies an area of 0.2mm² in a 0.18μm CMOS process, of which 0.073mm² is for the SAR ADC core.

Keywords

CMOS integrated circuits; analogue-digital conversion; image sensors; integrated circuit design; integrated circuit manufacture; power consumption; CMOS; QCIF image sensor; analog-to-digital converter; low-power successive-approximation-register ADC; on-chip bandgap voltage reference; power 21 muW; power 32 muW; power consumption; power pins; size 0.18 mum; tunable clock generator; ultra-low power image sensors; voltage 0.8 V; word length 8 bit; Arrays; CMOS integrated circuits; CMOS process; Capacitors; Clocks; Photonic band gap; Power demand;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2011 IEEE International Symposium on

Conference_Location

Rio de Janeiro

ISSN

0271-4302

Print_ISBN

978-1-4244-9473-6

Electronic_ISBN

0271-4302

Type

conf

DOI

10.1109/ISCAS.2011.5937697

Filename

5937697