Accelerated variation simulation through parameter reduction

Proper understanding of the effects of parameter variations in a circuit requires simulation; unfortunately, accurate variation simulation can hinder simulation performance. Even though the majority of interdie variations occur between four parameters (L, W, t_ox, V_fb) [1], this parameter set is still too big for efficient large-scale simulations. As these variations all affect threshold voltage (V_th), ΔV_th is often used as a substitute for variations [2], [3]. While a ΔV_th substitute offers vast improvement in runtime, it has a rarely-understood loss in quality. In this work, we demonstrate two methods that, when presented with a set of device variations (L, W, t_ox, V_fb) and a model, can simplify those variations into a reusable model that provides accelerated simulation. Our first method, approximate ΔV_gs superposition, offers an accelerated method to reduce process variations down a single, manageable ΔV_th-like parameter. Our second, reduced parameter method, preserves the effects of individual variations while lowering the runtime complexity. Instead of generating device attributes specific to the tested circuit, our method used a dynamic superposition approach to interpolate device parameters from a reduced-dimension lookup table. Both of our methods demonstrate significant runtime computation savings, with a low break-even point as compared to the original model. While the ΔV_gs approach does demonstrate a noticeable quality loss compared to the original model, our reduced parameter approach demonstrates minimal loss in quality.