A Novel Variation-Aware Interconnection Parasitic Extraction Method for 40nm Technology

Author

Ren Zheng ; Li Xi ; Shi Yanling ; Hu Shaojian ; Zhou Wei ; Chen Shoumian

Author_Institution

Dept. of Electr. Eng., East China Normal Univ., Shanghai, China

fYear

2012

fDate

27-30 May 2012

Firstpage

1

Lastpage

4

Abstract

In this paper, a novel technique is presented to perform variation-aware interconnection parasitic parameters extraction on 40nm process technology. Several kinds of test structure are designed for these extractions. Based on layouts of parasitic metal capacitors, 3D simulations are performed and typical Interconnection Technology Format (ITF) profile is extracted. Full mapping tests are made on these structures and distribution of measurements are analyzed. With the statistical data and process information attached, the statistical parameters are extracted using Principal Component Analysis Method. Finally, according to comparison of statistical data between simulations and measurements, the variation-aware ITF is proved accurate and necessary for the nano-scale IC process technology.

Keywords

capacitors; integrated circuit interconnections; nanoelectronics; principal component analysis; statistical analysis; full mapping test; nanoscale IC process technology; parasitic metal capacitor; principal component analysis method; size 40 nm; statistical data; statistical parameter; test structure; three-dimensional simulation; typical interconnection technology format profile; variation-aware ITF; variation-aware interconnection parasitic extraction method; variation-aware interconnection parasitic parameter extraction; Capacitors; Couplings; Integrated circuit interconnections; Integrated circuit modeling; Layout; Metals;

fLanguage

English

Publisher

ieee

Conference_Titel

Engineering and Technology (S-CET), 2012 Spring Congress on

Conference_Location

Xian

Print_ISBN

978-1-4577-1965-3

Type

conf

DOI

10.1109/SCET.2012.6341951

Filename

6341951