DocumentCode :
1989113
Title :
A new concept for high voltage MCCT with no J-FET resistance by using a very thin wafer
Author :
Iwamuro, N. ; Iwaana, T. ; Harada, Y. ; Onozawa, Y. ; Seki, Y.
Author_Institution :
Adv. Device Technol. Lab., Fuji Electr. Corp. Res. & Dev. Ltd., Matsumoto, Japan
fYear :
1997
fDate :
10-10 Dec. 1997
Firstpage :
351
Lastpage :
354
Abstract :
A high voltage non-punch-through MCCT with newly developed thyristor-centered cells was successfully fabricated for the first time. A 4.22 mm/spl square/ high voltage MCCT with its blocking voltage of 1460 V was fabricated using an inexpensive and an extremely thin bulk wafer of 200 /spl mu/m with low breakage rate of less than 4%. This low breakage rate can be attained by the improvement of wafer grinding method to smooth the wafer edge and so on. Less junction-FET resistance and the thin bulk wafer application are highly effective to achieve a superior electrical characteristic to the punch-through type device using an epi wafer.
Keywords :
MOS-controlled thyristors; grinding; semiconductor technology; 1460 V; J-FET resistance; MOS controlled cascode thyristor; blocking voltage; breakage rate; electrical characteristics; fabrication; grinding; high voltage nonpunch-through MCCT; thin bulk epi wafer; Annealing; Circuits; Degradation; Fabrication; Insulated gate bipolar transistors; Passivation; Switching loss; Temperature; Thyristors; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International
Conference_Location :
Washington, DC, USA
ISSN :
0163-1918
Print_ISBN :
0-7803-4100-7
Type :
conf
DOI :
10.1109/IEDM.1997.650397
Filename :
650397
Link To Document :
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