Addressing key challenges in 1T-DRAM: Retention time, scaling and variability — Using a novel design with GaP source-drain

We propose a vertical gate all around 1-transistor DRAM cell with silicon channel and gallium phosphide source drain (GaP-SD) as a viable alternative to the present 1T-1C DRAM technology. The valence band offset at GaP and Si interface helps to store more holes in the transistor body and thus improves the retention time by 2 order over conventional Si-SD 1T DRAM. By examining body thickness variability, we conclude that GaP-SD memory cell can withstand the performance degradation due to device variability to meet the ITRS retention time requirements. Finally the GaP-SD memory cell is optimized for scaled dimensions upto 20nm body thickness to establish its superiority at lower technology nodes.