DocumentCode
1989562
Title
Fault diagnosis and calibration of large analog circuits
Author
Starzyk, Janusz A. ; Dai, Hong
Author_Institution
Dept. of Electr. & Comput. Eng., Ohio Univ., Athens, OH, USA
fYear
1988
fDate
7-9 June 1988
Firstpage
941
Abstract
A method to test and calibrate linear circuits is proposed. A tested circuit is partitioned at nodes where the voltage measurements are taken. Test equations are formulated on the basis of Kirchoff´s current law equations at the partition points. This results in the Jacobian matrix with a sparse block structure. The test points selection and the element evaluation can be performed in parallel, reducing computation time and enhancing the test performance.<>
Keywords
analogue circuits; calibration; circuit analysis computing; fault location; linear network analysis; Jacobian matrix; Kirchoff´s current law equations; calibration; computation time; element evaluation; fault diagnosis; large analog circuits; linear circuits; partition points; sparse block structure; test performance; test points selection; voltage measurements; Analog circuits; Calibration; Circuit testing; Concurrent computing; Equations; Fault diagnosis; Jacobian matrices; Linear circuits; Performance evaluation; Voltage measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location
Espoo, Finland
Type
conf
DOI
10.1109/ISCAS.1988.15078
Filename
15078
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