Algorithms for the partitioning of applications containing variable duration tasks on reconfigurable architectures

Summary form only given. Many applications, especially in image processing, have variable execution times according to the nature of data to process. The implementation of low level processing in image processing (for example the detection of contours, labeling) in embedded architectures often uses specialized systems. We consider an architecture composed of a RISC processor linked to a dynamically reconfigurable circuit through a memory interface. To help to distribute processing with variable execution time on this architecture we present a partitioning approach based on a genetic algorithm.