DocumentCode
1989876
Title
Area Efficient Low-Power Static Explicit-Pulsed Flip-Flop with Local Feedback
Author
Yeo, K.-S. ; Goh, W.L. ; Phyu, M.-W.
Author_Institution
School of Electrical and Electronics Engineering, Nanyang Technological University, Singapore
fYear
2005
fDate
19-21 Dec. 2005
Firstpage
735
Lastpage
738
Abstract
In this paper, a static explicit-pulsed single/double edge-triggered flip-flop suitable for low-power application is presented. It offers energy savings by reduction unnecessary internal switching activities. All circuits are simulated in 0.18-μm CMOS technology with a supply voltage of 1.8V. The developed circuit provides up to 18.1% total gate-area reduction and also 19.4% improvement in the power-delay over the best performing flip-flop reported to-date.
Keywords
CMOS technology; Circuit simulation; Clocks; Delay effects; Energy consumption; Feedback; Flip-flops; Latches; Pulse generation; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits, 2005 IEEE Conference on
Print_ISBN
0-7803-9339-2
Type
conf
DOI
10.1109/EDSSC.2005.1635381
Filename
1635381
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