A Low-Energy Asynchronous FFT/IFFT Processor for Hearing Aid Applications

In this paper, we investigate the energy efficacy of the asynchronous (async) logic over its synchronous (sync) counterpart in a 128-point FFT/IFFT processor for low voltage (1.1V to 1.4V) energy-critical medium-to-low speed applications including hearing aids. Both async and sync designs are implemented using the same process (0.35μm CMOS) and having the same computational complexity. For the latter sync design, we consider both scenarios with and without the clock gating approach. Our async design features ∼23% and ∼39% lower energy compared to its sync counterpart with and without the clock gating approach respectively.