Title :
A cached system architecture dedicated for the system IO activity on a CPU board
Author :
Hsieh, Michael M. ; Wei, Tek C. ; Loo, W.V.
Author_Institution :
Sun Microsyst. Inc., Mountain View, CA, USA
Abstract :
The architecture of a cached IO subsystem on a CPU board of a high-performance workstation is described. The cached IO subsystem is intended to reduce the memory latency for IO activity and minimize the number of processor cycles stolen by IO traffic, to achieve a better balanced computer system in terms of both the CPU computation power and the system IO bandwidth. The model of the cached IO subsystem is shown to illustrate the system architecture. The discussion covers arbitration of system IO activity, the architecture of the virtual address accessed IO cache, the cache coherency algorithm, as well as the comparison of theoretical bounds of IO bandwidth and CPU degradation between different caching schemes
Keywords :
buffer storage; input-output programs; memory architecture; CPU board; CPU computation power; CPU degradation; IO activity; IO traffic; balanced computer system; cache coherency algorithm; cached IO subsystem; cached system architecture; high-performance workstation; memory latency; processor cycles; system IO bandwidth; theoretical bounds; virtual address accessed IO cache; Bandwidth; Central Processing Unit; Computer architecture; Delay; Ethernet networks; Hardware; Microprocessors; Power system modeling; System buses; Workstations;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63420
