Lateral DMOS design for ESD robustness

This paper presents the design of efficient ESD protection in lateral DMOS (LDMOS) power transistor. Using characterization of the LDMOS transistor under ESD conditions with various gate and drain clamps, the design for minimum power dissipation is established. The results show that for ESD regime of pulses the channel heating effects are minimum and that optimum ESD level can be achieved by driving the device into maximum possible MOS conduction. Based on these results, an empirical formula for effective ESD design is derived.