A dual-mode VCO based low-power synthesizer with optimized automatic frequency calibration for software-defined radio

A low power sigma-delta fractional-N frequency synthesizer for software-defined radio (SDR) implemented in a 0.13 μm CMOS process is presented, based on a dual-mode VCO (DMVCO) reconfigurable between wideband mode and quadrature mode, with optimized automatic frequency calibration (AFC). The proposed optimized AFC enables a more accurate band selection as well as a lower power for a dual-VCO PLL. A multi-phase counter (MPC) accelerates the calibration process without ruining the calibration accuracy. Simulated phase noise is -123 dBc/Hz at 1 MHz offset from a 1.8 GHz carrier. The spectral purity is better than 45 dBc from the output of mixer. The locking time of PLL is about 40 μs with an AFC time less than lOμs. The 0.4-6 GHz synthesizer consumes only 35 mW to 51 mW from a 1.2 V supply.