A simple radix-4 Booth encoded modulo 2n+1 multiplier

An area-efficient diminished-1 modulo 2ⁿ+1 multiplier with radix-4 modified Booth encoding is proposed. The proposed approach minimizes the number of Booth encoder and Booth decoder blocks required for partial product generation. Its correction factor is decomposed into a multiplier- dependent dynamic bias and a multiplier-independent static bias. The dynamic bias can be generated by hardwiring the outputs of the Booth encoder to appropriate bit positions, while the sum of the static bias and other multiplier-independent bias has been reduced to a simple binary word of alternate ones and zeros. For n = 40, the proposed multiplier achieves an area saving of 27% and a power reduction of 18.5% over the non- encoded modulo 2ⁿ+l multiplier. The proposed multiplier exhibits an area saving and an average power reduction of 52% and 62% respectively over the existing Booth encoded modulo 2ⁿ+l multiplier for the same n. The energy-delay product analysis indicates that the proposed multiplier provides an optimized trade-off between power consumption and delay.