• DocumentCode
    1990838
  • Title

    A unified optimization framework for simultaneous gate sizing and placement under density constraints

  • Author

    Cong, Jason ; Lee, John ; Luo, Guojie

  • Author_Institution
    Comput. Sci. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA
  • fYear
    2011
  • fDate
    15-18 May 2011
  • Firstpage
    1207
  • Lastpage
    1210
  • Abstract
    A unified optimization framework is presented for simultaneous gate sizing and placement. These processes are unified using Lagrangian multipliers, which synchronize the efforts of the gate sizing and placement subproblems. As far as we know, this is the first work that formulates and solves the simultaneous gate sizing and placement under area density constraints, which are handled by the quadratic penalty method. We show that this rigorous framework results in an algorithm that is faster than separate iterations of gate sizing and placement steps, and leads to more robust results for a set of benchmarks.
  • Keywords
    circuit optimisation; multiplying circuits; Lagrangian multiplier; area density constraint; density constraint; quadratic penalty method; simultaneous gate placement; simultaneous gate sizing; unified optimization framework; Algorithm design and analysis; Capacitance; Delay; Logic gates; Optimization; Runtime; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
  • Conference_Location
    Rio de Janeiro
  • ISSN
    0271-4302
  • Print_ISBN
    978-1-4244-9473-6
  • Electronic_ISBN
    0271-4302
  • Type

    conf

  • DOI
    10.1109/ISCAS.2011.5937786
  • Filename
    5937786