Low-power FIR digital filters using residue arithmetic

This paper demonstrates that residue arithmetic can result in implementation of low-power FIR digital filters. It is shown that, for word-lengths up to 32 bits, the power consumption of residue arithmetic-based FIR filters is dramatically less than two´s-complement-based FIR filters. The power reduction is possible since the use of residue arithmetic transforms the filtering problem into multiple smaller word-length filters for various moduli which are operated in parallel. These compact filters can be operated with a lower supply voltage for a specified sample speed, thus obtaining decreased power consumption compared to binary. Power reduction factors for residue arithmetic implementation become increasingly favorable as the system word-length is increased.