DocumentCode
1991075
Title
Compact Implementation of Skein-256 Hash Function on FPGA
Author
Kundi, Dure-Shahwar ; Aziz, Arshad
Author_Institution
Dept. of Electr. Eng., Nat. Univ. of Sci. & Technol., Islamabad, Pakistan
fYear
2012
fDate
27-30 May 2012
Firstpage
1
Lastpage
4
Abstract
In this paper we have presented a low-area design of Skein-256 hash function on Xilinx Virtex-5 FPGA. Skein is one of the 5 finalists of SHA-3 competition. Our implementation is utilizing only 527 slices and shows a throughput of 1.295 Gbps. Comparing our results with the previous published FPGA implementations of Skein-256, our design reports the best TPS of 2.457. High value of TPS shows the efficiency of our design.
Keywords
cryptography; field programmable gate arrays; logic design; FPGA; Skein-256 hash function; TPS; Xilinx Virtex-5; bit rate 1.295 Gbit/s; low area design; Algorithm design and analysis; Clocks; Field programmable gate arrays; Hardware; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Engineering and Technology (S-CET), 2012 Spring Congress on
Conference_Location
Xian
Print_ISBN
978-1-4577-1965-3
Type
conf
DOI
10.1109/SCET.2012.6342053
Filename
6342053
Link To Document