DocumentCode :
1991118
Title :
Symbolic model checking for real time systems using difference typed decision graphs
Author :
Ayadi, S. ; Robbana, R.
Author_Institution :
FST, Tunisia
fYear :
2003
fDate :
14-18 July 2003
Firstpage :
72
Abstract :
Summary form only given. In symbolic model checking of untimed systems, the general approach is based on BDDs (Binary Decision Diagrams) representation. Concurrently, TDGs (typed Decision Graphs) were proposed in another context, bring a better profit of capacity memory. However, the symbolic method do not easily generalize to models that contain variables ranging over noncountable domains like for example real-time systems where time is modeled using continuous real variables and the behavior of a system is specified using constraints on these variables. To solve the reachability problem for a timed system, there are very few results on how model checking is efficient, such as the technique of DDDs (Difference Decision Diagrams) representing difference constraints on clocks. But, it remains an open problem to find algorithms and data structures that work just as well for timed systems as BDDs do for untimed systems. We present a methodology for the symbolic model checker using a new technique of representation of timed systems: the DTDGs, Difference Typed Decision Graphs that is a combination of TDGs and DDDs. Then, our approach consists in analyzing timed systems symbolically, and describe the corresponding data structure (DTDGs) for representing the state space of a timed system. For that, we use timed graphs for the modelling of timed systems. This result allows us to analyse timed systems with both the discrete part of states and the associated timing information. Hence the motivation is about symbolic model checking for timed systems based on difference typed decision graphs.
Keywords :
binary decision diagrams; data structures; formal verification; reachability analysis; real-time systems; temporal logic; BDD; DDD; DTDG; TDG; binary decision diagram; data structure; difference constraint expression; difference decision diagram; difference typed decision graphs; model checking; reachability problem; real time systems; symbolic model checking; temporal logic; timed graph; timed system modelling; typed decision graph; Boolean functions; Clocks; Data structures; Information analysis; Logic; Real time systems; State-space methods; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Systems and Applications, 2003. Book of Abstracts. ACS/IEEE International Conference on
Conference_Location :
Tunis, Tunisia
Print_ISBN :
0-7803-7983-7
Type :
conf
DOI :
10.1109/AICCSA.2003.1227504
Filename :
1227504
Link To Document :
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