DocumentCode
1991179
Title
On latching probability of particle induced transients in combinational networks
Author
Liden, P. ; Dahlgren, P. ; Johansson, R. ; Karlsson, J.
Author_Institution
Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
fYear
1994
fDate
15-17 June 1994
Firstpage
340
Lastpage
349
Abstract
The question to what extent particle induced transients in combinational parts of a circuit propagate into memory elements is addressed in this paper An experimental method is presented in which the proportion of bit flips originating from heavy-ion hits in combinational logic is determined. It is proposed that a voltage pulse may only propagate through a limited number of transistor stages and still be latched. The proportion of all transients in combinational logic that were latched into registers was experimentally, estimated to be between 0.7/spl middot/10/sup -3/ and 2/spl middot/10/sup -3/ for a custom designed CMOS circuit. Very few multiple bit flips were observed during the experiments which indicates that the single bit flip model used in many high-level simulations is reasonable accurate.<>
Keywords
CMOS integrated circuits; circuit reliability; combinatorial circuits; flip-flops; logic testing; probability; CMOS circuit; bit flips; combinational logic; combinational networks; heavy-ion hits; high-level simulations; latching probability; memory elements; particle induced transients; transistor stages; voltage pulse; CMOS logic circuits; Circuit faults; Circuit simulation; Combinational circuits; Intelligent networks; Latches; Pulse generation; Semiconductor device modeling; Single event transient; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Fault-Tolerant Computing, 1994. FTCS-24. Digest of Papers., Twenty-Fourth International Symposium on
Conference_Location
Austin, TX, USA
Print_ISBN
0-8186-5520-8
Type
conf
DOI
10.1109/FTCS.1994.315626
Filename
315626
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