Architectural timing verification and test for super scalar processors

We address the problem of verification and testing of super scalar processors, from the point of view of correctness of [Bprogram execution time. Trace-driven architectural si[Bmulation methods are commonly used in current industrial practice to estimate cycles-per-instruction performance of a candidate processor organization, prior to actual implementation. We present a novel set of strategies for testing the timing correctness of processors as represented in an architectural timing model ("timer"). We focus on two main aspects of the theory: (a) deriving architectural test sequences to cover possible failure modes, defined in the context of a pipeline flow state transition fault model; and (b) deriving loop test kernels to verify steady-state (periodic) behavior of pipeline flow, against analytically predicted signatures. We develop the theory in the context of an example super scalar processor and its timer model.<>