Title :
A programmable logic array optimiser system (PLAOS) for VLSI design
Author :
Hadjinicolaou, M.G. ; Musgrave, G.
Author_Institution :
Dept. of Electr. & Electron., Brunel Univ., Uxbridge, UK
Abstract :
PLAOS is an integrated interactive software program that combines graphic display, Boolean personality matrix translation, and PLA folding to ensure more effective PLA designs. The program may be accommodated in any existing PLA procedure, so it does not require a major disruption to present methodology. The objectives are the attainment of compact area, low design, and ease of design. Symbolic layout generation for the PLA is treated in detail, and practical design algorithms for folding are discussed
Keywords :
VLSI; cellular arrays; circuit layout CAD; integrated circuit technology; logic CAD; logic arrays; Boolean personality matrix translation; CAD; PLA folding; PLA optimiser system; PLAOS; VLSI design; computer aided design; design algorithms; graphic display; integrated interactive software program; programmable logic array; symbolic layout generation; Algorithm design and analysis; Consumer electronics; Design automation; Design optimization; Input variables; Logic arrays; Logic design; Programmable logic arrays; Simulated annealing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1989., Proceedings of the 32nd Midwest Symposium on
Conference_Location :
Champaign, IL
DOI :
10.1109/MWSCAS.1989.102038
