Title :
A high-throughput LDPC decoder architecture for high-rate WPAN systems
Author :
Baek, Kyung-Il ; Lee, Hanho ; Choi, Chang-Seok ; Kim, Sangmin ; Sobelman, Gerald E.
Author_Institution :
Dept. of Inf. & Commun. Eng., Inha Univ., Incheon, South Korea
Abstract :
This paper presents a high-throughput memory- efficient decoder architecture for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes in the high-rate wireless personal area network applications. Two novel techniques which can apply to our selected QC-LDPC codes are proposed, including four-parallel block layered decoding architecture and simplification of the switch networks. The proposed architecture based on a block parallel decoding scheme replaces a crossbar- based interconnect network with a fixed wire network for a switch network. In addition, two-stage pipelining is used to improve the clock speed. A 672-bit, rate-1/2 LDPC decoder is implemented using 90 nm CMOS technology. The design achieves an information throughput of 1.45 Gbps at a clock speed of 285 MHz with a maximum of 16 iterations.
Keywords :
CMOS integrated circuits; cyclic codes; memory architecture; parity check codes; personal area networks; CMOS technology; QC-LDPC code; block parallel decoding scheme; fixed wire network; four-parallel block layered decoding architecture; high rate WPAN system; high rate wireless personal area network application; high throughput LDPC decoder architecture; high throughput memory efficient decoder architecture; interconnect network; quasi-cyclic low density parity check code; switch network; two stage pipelining; Clocks; Computer architecture; Decoding; Iterative decoding; Pipeline processing; Throughput;
Conference_Titel :
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location :
Rio de Janeiro
Print_ISBN :
978-1-4244-9473-6
Electronic_ISBN :
0271-4302
DOI :
10.1109/ISCAS.2011.5937812