DocumentCode :
1991516
Title :
QC-LDPC Decoding Architecture based on Stride Scheduling
Author :
Kim, Bongjin ; Park, In-Cheol
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea
fYear :
2011
fDate :
15-18 May 2011
Firstpage :
1319
Lastpage :
1322
Abstract :
In this paper, an area-efficient decoder architecture is proposed for the quasi-cyclic low-density parity check (QC-LDPC) codes specified in the WiMAX 802.16e standard. In order to achieve low area and maximize hardware utilization, the decoder utilizes 4 decoding function units, which is the greatest common divisor of the expansion factors. Furthermore, the decoder adopts a novel scheduling scheme, named as stride scheduling, to remove the conventional flexible permutation network and also minimize the number of memory accesses. The synthesized decoder costs 49K of logic gates and 54,144 bits of memory, while maintaining the throughput over the requirement of the WiMAX.
Keywords :
WiMax; codecs; decoding; parity check codes; scheduling; QC-LDPC decoding architecture; WiMAX 802.16e standard; area-efficient decoder architecture; flexible permutation network; quasi-cyclic low-density parity check; scheduling scheme; stride scheduling; synthesized decoder costs; Complexity theory; Decoding; Parallel processing; Parity check codes; Switches; Throughput; WiMAX;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location :
Rio de Janeiro
ISSN :
0271-4302
Print_ISBN :
978-1-4244-9473-6
Electronic_ISBN :
0271-4302
Type :
conf
DOI :
10.1109/ISCAS.2011.5937814
Filename :
5937814
Link To Document :
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