DocumentCode
1991755
Title
Verification techniques for deadlock and real time constraint violation
Author
Ouni, B. ; Sayadi, N. ; Mtibaa, A. ; Zitouni, A. ; Abid, M.
Author_Institution
Lab. of Electron. & Microelectron., Fac. of Sci. Monastir, Tunisia
fYear
2003
fDate
14-18 July 2003
Firstpage
100
Abstract
Summary form only given. Design automation depends on high-level modelling and system specification. Such modelling and specification requires a long time. Therefore designers need to introduce verification techniques in order to avoid several problems in codesign. We present two verification techniques based on the discrete event model (DE) in order to allow the automatic verification of deadlock and real time constraint violation.
Keywords
automatic programming; discrete event systems; program verification; real-time systems; system recovery; systems analysis; deadlock verification; design automation; discrete event model; high-level modeling; real time constraint violation verification; system specification; verification techniques; Design automation; Laboratories; Microelectronics; System recovery;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Systems and Applications, 2003. Book of Abstracts. ACS/IEEE International Conference on
Conference_Location
Tunis, Tunisia
Print_ISBN
0-7803-7983-7
Type
conf
DOI
10.1109/AICCSA.2003.1227532
Filename
1227532
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