A low-power third-order ΔΣ modulator using a single operational amplifier

An architecture for low-power ΔΣ modulators suitable for high-resolution portable sensor systems is presented. The circuit uses a single operational amplifier to achieve a third-order noise shaping. The two-stage op-amp employs a boosting technique that increases by 5 the slew-rate. The circuit, simulated at the transistor level using a conventional 0.18-μm CMOS technology, obtains a peak SNDR of 88 dB over an input signal bandwidth of 100 kHz. The simulated power consumption is 125 μW with a 1.5-V supply voltage. The achieved Figure of Merit (FoM) is 31 fJ/conversion-level.