Noise coupling due to through silicon vias (TSVs) in 3-D integrated circuits

Three-dimensional (3-D) integration is a promising technology to alleviate the interconnect bottleneck by stacking multiple dies in a monolithic fashion. Both power dissipation and delay can be reduced by utilizing the third dimension where through silicon vias (TSVs) are used for vertical communication. Characteristics of switching noise that couples to a sensitive device due to a TSV are investigated in this paper. A model is developed to evaluate the noise performance of a TSV. Several noise isolation strategies are also discussed. Ignoring noise characteristics during the TSV placement process produces a poor 3-D circuit with high susceptibility to switching noise.