A 1.2V 6.4GHz 181ps 64-bit CD domino adder with DLL measurement technique

Author

Wang, Yu-Shun ; Hsieh, Min-Han ; Liu, Chia-Ming ; Wu, Yi-Chi ; Lin, Bing-Feng ; Chiu, Hsien-Chen ; Chen, Charlie Chung-Ping

Author_Institution

Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2011

fDate

15-18 May 2011

Firstpage

1423

Lastpage

1426

Abstract

A novel 64-bit hybrid radix-4 sparse-4 tree adder using clock-delayed (CD) footless domino logic is proposed. The adder operates at 6.4GHz with 181ps latency and it consumes 840mW at 1.2V in a standard 90nm CMOS technology. The adder latency is accurately measured by the programmable clock generated from delay-locked loop (DLL). Pseudo-exhaustive testing is applied so that all testable faults in this 64-bit adder are detected by just 23K patterns. This at-speed self testing technique is very useful for speed binning of high performance CPU.

Keywords

CMOS logic circuits; adders; delay lock loops; field effect MMIC; logic testing; microwave measurement; CD domino adder; CMOS technology; CPU; DLL measurement technique; at-speed self testing technique; bit rate 181 bit/s; clock-delayed footless domino logic; delay-locked loop; frequency 6.4 GHz; hybrid radix-4 sparse-4 tree adder; power 840 mW; programmable clock; pseudo-exhaustive testing; size 90 nm; voltage 1.2 V; word length 64 bit; Adders; Circuit faults; Clocks; Delay; Integrated circuit interconnections; Testing; Wires; clock-delayed footless domino logic; delay lock loop (DLL); domino adder; pseudo-exhaustive testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2011 IEEE International Symposium on

Conference_Location

Rio de Janeiro

ISSN

0271-4302

Print_ISBN

978-1-4244-9473-6

Electronic_ISBN

0271-4302

Type

conf

DOI

10.1109/ISCAS.2011.5937840

Filename

5937840