Automated translation of digital logic equations into VHDL code

A method for the automated translation of finite state machines from state table form to VHDL code is described. To do this, algorithms for reducing the state machine to simplest form, for making state assignments, for producing minimal logic equations to represent the state machine, and for producing VHDL code which describes the intended circuit are needed. Various algorithms were examined, and a prototype program was written to perform this translation